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1 ltc1404 1404fa v cc a in v ref gnd v ss conv clk d out mpu p1.4 p1.3 p1.2 ltc1404 + 0.1 f 10 f + 0.1 f 10 f* *avx tpsd106m035r0300 ref out 2.43v analog input (0v to 4.096v) serial data link 5v ltc1404 ?ta01 typical applicatio u applicatio s u descriptio u features power consumption vs sample rate single 5v supply, 600khz, 12-bit sampling a/d converter the ltc 1404 is a complete 600ksps, 12-bit a/d con- verter which draws only 75mw from 5v or 5v supplies. this easy-to-use device comes complete with a 160ns sample-and-hold and a precision reference. unipolar and bipolar conversion modes add to the flexibility of the adc. the ltc1404 has two power saving modes: nap and sleep. in nap mode, it consumes only 7.5mw of power and can wake up and convert immediately. in the sleep mode, it consumes 60 w of power typically. upon power- up from sleep mode, a reference ready (refrdy) signal is available in the serial data word to indicate that the reference has settled and the chip is ready to convert. the ltc1404 converts 0v to 4.096v unipolar inputs from a single 5v supply and 2.048v bipolar inputs from 5v supplies. maximum dc specs include 1lsb inl, 1lsb dnl and 45ppm/ c full-scale drift over temperature. guaranteed ac performance includes 69db s/(n + d) and 76db thd at an input frequency of 100khz over temperature. the 3-wire serial port allows compact and efficient data transfer to a wide range of microprocessors, microcontrollers and dsps. complete 12-bit adc in so-8 single supply 5v or 5v operation sample rate: 600ksps power dissipation: 75mw (typ) 72db s/(n + d) and 80db thd at nyquist no missing codes over temperature nap mode with instant wake-up: 7.5mw sleep mode: 60 w high impedance analog input input range (1mv/lsb): 0v to 4.096v or 2.048v internal reference can be overdriven externally 3-wire interface to dsps and processors (spi and microwire tm compatible) high speed data acquisition digital signal processing multiplexed data acquisition systems audio and telecom processing digital radio spectrum analysis low power and battery-operated systems handheld or portable instruments sample rate (hz) 0.01 supply current (ma) 100 10 1 0.1 0.01 0.001 10 1k 1m ltc1404 ?ta02 0.1 1 100 10k 100k normal conversion 9.6mhz clock sleep mode between conversion nap mode between conversion complete so-8, 12-bit, 600ksps adc with shutdown , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
2 ltc1404 1404fa the denotes specifications which apply over the full operating temperature range, unless otherwise noted specifications are at t a = 25 c. v cc = 5v, f sample = 600khz, t r = t f = 5ns, unless otherwise specified. absolute m axi m u m ratings w ww u (notes 1, 2) supply voltage (v cc ) ................................................. 7v negative supply voltage (v ss ) ................... 6v to gnd total supply voltage (v cc to v ss ) bipolar operation only ........................................ 12v analog input voltage (note 3) unipolar operation .................. 0.3v to (v cc + 0.3v) bipolar operation........... (v ss ?0.3v) to (v cc + 0.3v) digital input voltage (note 4) unipolar operation ................................ 0.3v to 12v bipolar operation.........................(v ss ?0.3v) to 12v digital output voltage unipolar operation .................. 0.3v to (v cc + 0.3v) bipolar operation........... (v ss ?0.3v) to (v cc + 0.3v) power dissipation .............................................. 300mw operating ambient temperature range ltc1404c ............................................... 0 c to 70 c ltc1404i ............................................ 40 c to 85 c junction temperature .......................................... 125 c storage temperature range ................. 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c package/order i n for m atio n w u u symbol parameter conditions min typ max units v cc positive supply voltage unipolar 4.75 5.25 v bipolar 4.75 5.25 v v ss negative supply voltage bipolar only 2.45 5.25 v i cc positive supply current f sample = 600ksps 15 30 ma nap mode 1.3 3.0 ma sleep mode 8.0 20.0 a i ss negative supply current f sample = 600ksps, v ss = 5v 0.2 0.6 ma nap mode 0.2 0.5 ma sleep mode 410 a p d power dissipation f sample = 600ksps 75 160 mw nap mode 7.5 20 mw sleep mode 60 150 w symbol parameter conditions min typ max units v in analog input range 4.75v v cc 5.25v (unipolar) 0 to 4.096 v 4.75v v cc 5.25v, 5.25v v ss 2.45v (bipolar) 0 to 2.048 v i in analog input leakage current during conversions (hold mode) 1 a c in analog input capacitance between conversions (sample mode) 45 pf during conversions (hold mode) 5 pf put u i a a u log power require e ts w u top view v cc a in v ref gnd v ss conv clk d out s8 package 8-lead plastic so 1 2 3 4 8 7 6 5 t jmax = 125 c, ja = 130 c/w order part number s8 part marking consult ltc marketing for parts specified with wider operating temperature ranges. ltc1404cs8 ltc1404is8 1404 1404i order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ the denotes specifications which apply over the full operating temperature range, unless otherwise noted specifications are at t a = 25 c. v cc = 5v, f sample = 600khz, t r = t f = 5ns, unless otherwise specified.
3 ltc1404 1404fa parameter conditions min typ max units resolution (no missing codes) 12 bits integral linearity error (note 7) 1lsb differential linearity error 1lsb offset error (note 8) 6lsb 8lsb full-scale error 15 lsb full-scale tempco i out(ref) = 0 10 45 ppm/ c cc hara terist ics co u verter symbol parameter conditions min typ max units s/(n + d) signal-to-noise 100khz input signal 69 72 db 300khz input signal 72 db thd total harmonic distortion 100khz input signal ?2 ?6 db up to 5th harmonic 300khz input signal 80 db peak harmonic or 100khz input signal ?4 ?6 db spurious noise 300khz input signal 82 db imd intermodulation distortion f in1 = 99.17khz, f in2 = 102.69khz 82 db f in1 = 298.68khz, f in2 = 304.83khz 70 db full power bandwidth 5 mhz full linear bandwidth (s/(n + d) 68db) 1 mhz accuracy ic dy u w a i ter al refere ce characteristics u uu parameter conditions min typ max units v ref output voltage i out = 0 2.410 2.430 2.450 v v ref output tempco i out = 0 10 45 ppm/ c v ref line regulation 4.75v v cc 5.25v 0.5 lsb/ v 5.25v v ss 0v 0.01 lsb/ v v ref load regulation 0 ? i out ? 1ma 1 lsb/ma v ref wake-up time from sleep mode c vref = 10 f 2.5 ms symbol parameter conditions min typ max units v ih high level input voltage v cc = 5.25v 2.0 v v il low level input voltage v cc = 4.75v 0.8 v i in digital input current v in = 0v to v cc 10 a c in digital input capacitance 5pf v oh high level output voltage v cc = 4.75v, i o = 10 a 4.7 v v cc = 4.75v, i o = 200 a 4.0 v v ol low level output voltage v cc = 4.75v, i o = 160 a 0.05 v v cc = 4.75v, i o = 1.6ma 0.10 0.4 v digital i puts a n d outputs u u the denotes specifications which apply over the full operating temperature range, unless otherwise noted specifications are at t a = 25 c. v cc = 5v, f sample = 600khz, t r = t f = 5ns, unless otherwise specified. the denotes specifications which apply over the full operating temperature range, unless otherwise noted specifications are at t a = 25 c. with internal reference v cc = 5v, f sample = 600khz, t r = t f = 5ns, unless otherwise specified (note 6). the denotes specifications which apply over the full operating temperature range, unless otherwise noted specifications are at t a = 25 c. v cc = 5v, f sample = 600khz, t r = t f = 5ns, unless otherwise specified. the denotes specifications which apply over the full operating temperature range, unless otherwise noted specifications are at t a = 25 c. v cc = 5v, v ss = ?v, f sample = 600khz.
4 ltc1404 1404fa digital i puts a n d outputs u u symbol parameter conditions min typ max units i oz hi-z output leakage d out v out = 0v to v cc 10 a c oz hi-z output capacitance d out 15 pf i source output source current v out = 0v 10 ma i sink output sink current v out = v cc 10 ma ti i g characteristics w u note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd. note 3: when these pin voltages are taken below v ss (ground for unipolar mode) or above v cc , they will be clamped by internal diodes. this product can handle input currents greater than 60ma without latch-up if the pin is driven below v ss (ground for unipolar mode) or above v cc . note 4: when these pin voltages are taken below v ss (ground for unipolar mode), they will be clamped by internal diodes. this product can handle input currents greater than 60ma without latch-up if the pin is driven below v ss (ground for unipolar mode). these pins are not clamped to v cc . note 5: guaranteed by design, not subject to test. note 6: linearity, offset and full-scale specifications apply for unipolar and bipolar modes. note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 8: bipolar offset is the offset voltage measured from 0.5lsb when the output code flickers between 0000 0000 0000 and 1111 1111 1111. note 9: the rising edge of conv starts a conversion. if conv returns low at a bit decision point during the conversion, it can create small errors. for best performance, ensure that conv returns low either within 100ns after the conversion starts (i.e., before the first bit decision) or after the 14 clock cycles. (figure 13 timing diagram). note 10: if this timing specification is not met, the device may not respond to a request for a conversion. to recover from this condition a nap request is required. symbol parameter conditions min typ max units f sample(max) maximum sampling frequency 600 khz t conv conversion time f clk = 9.6mhz 1.36 s t acq acquisition time (unipolar mode) 200 ns (bipolar mode v ss = 5v) 160 ns f clk clk frequency 0.1 9.6 mhz t clk clk pulse width (notes 5 and 10) 40 ns t wk(nap) time to wake up from nap mode 350 ns t 1 clk pulse width to return to active mode 40 ns t 2 conv to clk setup time 70 ns t 3 conv after leading clk 0ns t 4 conv pulse width (note 9) 40 ns t 5 time from clk to sample mode 60 ns t 6 aperture delay of sample-and-hold jitter < 50ps 40 ns t 7 minimum delay between conversion (unipolar mode) (note 5) 220 310 ns (bipolar mode v ss = 5v) 180 300 ns t 8 delay time, clk to d out valid c load = 20pf 40 70 ns t 9 delay time, clk to d out hi-z c load = 20pf 40 70 ns t 10 time from previous data remains valid after clk c load = 20pf 10 30 ns t 11 minimum time between nap/sleep request to wake up request (notes 5 and 10) 50 ns the denotes specifications which apply over the full operating temperature range, unless otherwise noted specifications are at t a = 25 c. v cc = 5v, f sample = 600khz, t r = t f = 5ns, unless otherwise specified. the denotes specifications which apply over the full operating temperature range, unless otherwise noted specifications are at t a = 25 c. v cc = 5v, f sample = 600khz, t r = t f = 5ns, unless otherwise specified. see figures 12, 13, 14.
5 ltc1404 1404fa typical perfor m a n ce characteristics u w bipolar mode differential nonlinearity vs output code output code 2048 differential nonlinearity (lsbs) 2048 1404 g03 1024 0 1024 1.00 0.75 0.50 0.25 0 0.25 0.50 0.75 1.00 1536 512 512 1536 f sample = 600khz output code 0 differential nonlinearity (lsbs) 4096 1404 g01 1024 2048 3072 1.00 0.75 0.50 0.25 0 0.25 0.50 0.75 1.00 512 1536 2560 3584 f sample = 600khz unipolar mode differential nonlinearity vs output code output code 0 integral nonlinearity (lsbs) 4096 1404 g02 1024 2048 3072 1.00 0.75 0.50 0.25 0 0.25 0.50 0.75 1.00 512 1536 2560 3584 f sample = 600khz unipolar mode integral nonlinearity vs output code unipolar mode 4096 nonaverage fft with 300khz signal unipolar mode 4096 nonaverage fft with 100khz signal output code 2048 integral nonlinearity (lsbs) 2048 1404 g04 1024 0 1024 1.00 0.75 0.50 0.25 0 0.25 0.50 0.75 1.00 1536 512 512 1536 f sample = 600khz bipolar mode integral nonlinearity vs output code unipolar mode enob and signal/(noise + distortion) vs input frequency input frequency (khz) 10 effective number of bits signal/(noise + distortion) (db) 12 11 10 9 8 7 6 5 4 3 2 1 0 74 68 62 56 50 100 1000 1404 g07 f sample = 600khz nyquist frequency input frequency (khz) 80 70 60 50 40 30 20 10 0 100 1404 g08 10 1000 signal-to-noise ratio (db) f sample = 600khz input frequency (khz) 80 70 60 50 40 30 20 10 0 100 1404 g09 10 1000 signal-to-noise ratio (db) f sample = 600khz unipolar mode signal-to-noise ratio (without harmonics) vs input frequency bipolar mode signal-to-noise ratio (without harmonics) vs input frequency frequency (khz) 0 60 90 120 150 180 210 240 270 300 amplitude (db) 1404 g05 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 30 f sample = 600khz f in = 99.1699khz sinad = 71db thd = ?7db frequency (khz) 0 60 90 120 150 180 210 240 270 300 amplitude (db) 1404 g06 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 30 f sample = 600khz f in = 298.681khz sinad = 71db thd = 73db
6 ltc1404 1404fa typical perfor m a n ce characteristics u w frequency (khz) 0 140 160 180 200 220 240 260 280 300 amplitude (db) 1404 g12 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 20 40 60 80 100 120 f sample = 600khz fa = 298.6816406khz fb = 304.8339844khz fb 2fa + fb 2fb ?fa 3fb fa + fb 2fa 2fb fa 3fa unipolar mode intermodulation distortion plot at 300khz input frequency (khz) 10 amplitude (db below the fundamental) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 100 1000 1404 g10 f sample = 600khz thd 3rd harmonic 2nd harmonic unipolar mode distortion vs input frequency unipolar mode intermodulation distortion plot at 100khz frequency (khz) 0 60 120 150 210 270 30 90 180 240 300 amplitude (db) 1404 g11 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 f sample = 600khz fa = 99.16992188khz fb = 102.6855469khz fa fb 2fb 2fa ?fb 2fa bipolar mode intermodulation distortion plot at 300khz frequency (khz) 0 140 160 180 200 220 240 260 280 300 amplitude (db) 1404 g12 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 20 40 60 80 100 120 f sample = 600khz fa = 298.6816406khz fb = 304.8339844khz fb 2fa + fb 2fb ?fa 2fb + fa 3fb fa + fb 2fb 3fa 2fa fb ?fa fa
7 ltc1404 1404fa input frequency (khz) 10 spurious-free dynamic range (db) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 100 1000 1404 g16 f sample = 600khz typical perfor m a n ce characteristics u w unipolar mode peak harmonic or spurious noise vs input frequency bipolar mode power supply feedthrough vs ripple frequency temperature ( c) ?0 reference voltage (v) 2.440 2.438 2.436 2.434 2.432 2.430 2.428 2.426 2.424 2.422 2.420 ?5 0 25 1404 g20 50 75 100 125 load current (ma) ? reference voltage (v) ? ? ? 1 1404 g21 ? ? ? ? 0 2.45 2.44 2.43 2.42 2.41 2.40 2.39 reference voltage vs temperature reference voltage vs load current source resistance ( ? ) 10 acquisition time ( s) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 100 1k 10k 1404 g22 t a = 25 c acquisition time vs source impedance unipolar mode power supply feedthrough vs ripple frequency input frequency (khz) 10 spurious-free dynamic range (db) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 100 1000 1404 g17 f sample = 600khz bipolar mode peak harmonic or spurious noise vs input frequency input frequency (khz) 80 70 60 50 40 30 20 10 0 100 1404 g14 10 1000 signal/(noise + distortion) (db) f sample = 600khz v in = 0db v in = 20db v in = 60db unipolar mode s/(n + d) vs input frequency and amplitude input frequency (khz) 80 70 60 50 40 30 20 10 0 100 1404 g15 10 1000 signal/(noise + distortion) (db) f sample = 600khz v in = 0db v in = 20db v in = 60db bipolar mode s/(n + d) vs input frequency and amplitude ripple frequency (khz) 1 power supply feedthrough (db) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 10 100 1000 1404 g19 a in = 0db a in frequency = 100khz f sample = 600khz v ss (v ripple = 10mv) v cc (v ripple = 1mv) ripple frequency (khz) 1 power supply feedthrough (db) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 10 100 1000 1404 g18 a in = 0db a in frequency = 100khz f sample = 600khz v cc (v ripple = 1mv)
8 ltc1404 1404fa typical perfor m a n ce characteristics u w unipolar mode v cc supply current vs temperature temperature ( c) ?0 v cc supply current (ma) 20 15 10 5 0 ?5 0 25 1404 g23 50 75 100 125 f sample = 600khz temperature ( c) ?0 v cc supply current (ma) v ss supply current ( a) 15.0 12.5 10.0 7.5 5.0 2.5 0 300 250 200 150 100 50 0 ?5 0 25 1404 g24 50 75 100 125 v cc current v ss current f sample = 600khz bipolar mode supply current vs temperature pi n fu n ctio n s uuu clk (pin 6): clock. this clock synchronizes the serial data transfer. a minimum clk pulse of 40ns signals the adc to wake up from nap or sleep mode. conv (pin 7): conversion start signal. this active high signal starts a conversion on its rising edge. keeping clk low and pulsing conv two/four times will put the adc into nap/sleep mode. v ss (pin 8): negative supply. 5v for bipolar operation. bypass to gnd with 10 f tantalum in parallel with 0.1 f ceramic. v ss should be tied to gnd for unipolar operation. v cc (pin 1): positive supply, 5v. bypass to gnd (10 f tantalum in parallel with 0.1 f ceramic). a in (pin 2): analog input. 0v to 4.096v (unipolar), 2.048v (bipolar). v ref (pin 3): 2.43v reference output. bypass to gnd (10 f tantalum in parallel with 0.1 f ceramic). gnd (pin 4): ground. gnd should be tied directly to an analog ground plane. d out (pin 5): the a/d conversion result is shifted out from this pin.
9 ltc1404 1404fa fu n ctio n al block diagra uu w 1404 bd 12-bit capacitive dac comp successive approximation register/parallel to serial converter zeroing switch control logic 2.43v ref d out v cc conv clk v ref a in c sample 12 gnd v ss test circuits 1404 tc01 d out d out 3k 3k c load c load hi-z to v oh v ol to v oh v oh to hi-z hi-z to v ol v oh to v ol v ol to hi-z 5v
10 ltc1404 1404fa applicatio n s i n for m atio n wu u u dynamic performance the ltc1404 has excellent high speed sampling capabil- ity. fft (fast fourier transform) test techniques are used to test the adc? frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algo- rithm, the adc? spectral content can be examined for frequencies outside the fundamental. figure 2a shows a typical ltc1404 fft plot. conversion details the ltc1404 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit serial output based on a precision internal reference. the control logic provides easy inter- face to microprocessors and dsps through 3-wire con- nections. a rising edge on the conv input starts a conversion. at the start of a conversion the successive approximation regis- ter (sar) is reset. once a conversion cycle has begun, it cannot be restarted. during conversion, the internal 12-bit capacitive dac output is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb). referring to figure 1, the a in input connects to the sample-and-hold capacitor during the acquired phase and the comparator offset is nulled by the feedback switch. in this acquire phase, it typically takes 160ns for the sample-and-hold capacitor to acquire the analog signal. during the convert phase, the comparator feedback switch opens, putting the comparator into the compare mode. the input switches connect c sample to ground, injecting the analog input charge onto the summing junction. this input charge is successively compared with the binary-weighted charges supplied by the capacitive dac. bit decisions are made by the high speed comparator. at the end of a conversion, the dac output balances the a in input charge. the sar contents (a 12-bit data word) which represent the input voltage, are presented through the serial pin d out . 1404 f01 sample d out c dac v dac dac a in c sample + comp s a r sample s1 hold figure 1. a in input frequency (khz) 0 60 90 120 150 180 210 240 270 300 amplitude (db) 1404 f02a 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 30 f sample = 600khz f in = 99.169khz sinad = 72db thd = 88db figure 2a. ltc1404 nonaveraged, 4096 point fft plot with 100khz input frequency in bipolar mode figure 2b. ltc1404 nonaveraged, 4096 point fft plot with 300khz input frequency in bipolar mode frequency (khz) 0 60 90 120 150 180 210 240 270 300 amplitude (db) 1404 f02b 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 30 f sample = 600khz f in = 298.681khz sinad = 71db thd = 84db
11 ltc1404 1404fa applicatio n s i n for m atio n wu u u signal-to-noise ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. the output is band limited to frequencies from dc to half the sampling frequency. figure 2a shows a typical spectral content with a 600khz sampling rate and a 100khz input. the dynamic perfor- mance is excellent for input frequencies up to the nyquist limit of 300khz as shown in figure 2b. effective number of bits the effective number of bits (enobs) is a measurement of the effective resolution of an adc and is directly related to the s/(n + d) by the equation: n sn d = + () /. . 176 602 where n is the effective number of bits of resolution and s/(n + d) is expressed in db. at the maximum sampling rate of 600khz, the ltc1404 maintains very good enobs up to the nyquist input frequency of 300khz (refer to figure 3). total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half of the sampling frequency. thd is expressed as: thd vvv vn v = +++? 20 234 1 222 2 log where v1 is the rms amplitude of the fundamental fre- quency and v2 through vn are the amplitudes of the second through nth harmonics. thd vs input frequency is shown in figure 4. the ltc1404 has good distortion performance up to the nyquist frequency and beyond. input frequency (hz) 10k amplitude (db below the fundamental) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 100k 1m 1404 f04 f sample = 600khz 3rd harmonic thd 2nd harmonic figure 4. distortion vs input frequency in bipolar mode intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. input frequency (hz) 10k effective number of bits signal/(noise + distortion) (db) 12 11 10 9 8 7 6 5 4 3 2 1 0 74 68 62 56 50 100k 1m 1404 f03 nyquist frequency f sample = 600khz figure 3. effective bits and signal-to-noise + distortion vs input frequency in bipolar mode
12 ltc1404 1404fa applicatio n s i n for m atio n wu u u if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. for example, the 2nd order imd terms include (fa + fb) and (fa ?fb) while the 3rd order imd terms includes (2fa + fb), (2fa ?fb), (fa + 2fb) and (fa ?2fb). if the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order imd products can be expressed by the following formula. imd fa fb fa fb () = 20log amplitude at ( ) amplitude at fa figure 5 shows the imd performance at a 100khz input. figure 5. intermodulation distortion plot in bipolar mode frequency (khz) 0 40 80 100 140 180 20 60 120 160 220 200 240 260 280 300 amplitude (db) 1404 f05 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 f sample = 600khz fa = 99.16992188khz fb = 102.6855469khz fa fb 3fa 2fb ?fa 2fa ?fb 2fa + fb 2fa 3fb fa + fb 2fb 2fb + fa peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spec- tral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full-scale input signal. full power and full linear bandwidth the full power bandwidth is the input frequency at which the amplitude of the reconstructed fundamental is re- duced by 3db for a full-scale input signal. the full linear bandwidth is the input frequency at which the s/(n + d) has dropped to 68db (11 effective bits). the ltc1404 has been designed to optimize input bandwidth, allowing the adc to undersample input signals with fre- quencies above the converter? nyquist frequency. the noise floor stays very low at high frequencies; s/(n + d) becomes dominated by distortion at frequencies far be- yond nyquist. driving the analog input the analog input of the ltc1404 is easy to drive. it draws only one small current spike while charging the sample- and-hold capacitor at the end of a conversion. during conversion, the analog input draws only a small leakage current. the only requirement is that the amplifier driving the analog input must settle after the small current spike before the next conversion starts. any op amp that settles in 160ns to small load current transient will allow maxi- mum speed operation. if a slower op amp is used, more settling time can be provided by increasing the time between conversions. suitable devices capable of driving the adc? a in input include the lt 1360 and the lt1363 op amps. the ltc1404 comes with a built-in unipolar/bipolar detec- tion circuit. if the v ss potential is forced below gnd, the internal circuitry will automatically switch to bipolar mode. the following list is a summary of the op amps that are suitable for driving the ltc1404, more detailed informa- tion is available in the linear technology databooks or the linear technology web site. lt 1215/lt1216: dual and quad 23mhz, 50v/ s single supply op amps. single 5v to 15v supplies, 6.6ma specifications, 90ns settling to 0.5lsb. lt1223: 100mhz video current feedback amplifier. 5v to 15v supplies, 6ma supply current. low distortion up to and above 600khz. low noise. good for ac applica- tions. lt1227: 140mhz video current feedback amplifier. 5v to 15v supplies, 10ma supply current. lowest distor- tion at frequencies above 600khz. low noise. best for ac applications.
13 ltc1404 1404fa applicatio n s i n for m atio n wu u u lt1229/lt1230: dual and quad 100mhz current feedback amplifiers. 2v to 15v supplies, 6ma supply current each amplifier. low noise. good ac specs. lt1360: 37mhz voltage feedback amplifier. 5v to 15v supplies. 3.8ma supply current. good ac and dc specs. 70ns settling to 0.5lsb. lt1363: 50mhz, 450v/ s op amps. 5v to 15v supplies. 6.3ma supply current. good ac and dc specs. 60ns settling to 0.5lsb. lt1364/lt1365: dual and quad 50mhz, 450v/ s op amps. 5v to 15v supplies, 6.3ma supply current per amplifier. 60ns settling to 0.5lsb. internal reference the ltc1404 has an on-chip, temperature compensated, curvature corrected, bandgap reference, which is factory trimmed to 2.43v. it is internally connected to the dac and is available at pin 3 to provide up to 1ma of current to an external load. for minimum code transition noise, the reference output should be decoupled with a capacitor to filter wideband noise from the reference (10 f tantalum in parallel with a 0.1 f ceramic). the v ref pin can be driven with a dac or other means to provide input span adjust- ment in bipolar mode. the v ref pin must be driven to at least 2.46v to prevent conflict with the internal reference. the reference should not be driven to more than 5v. figure 6 shows an lt 1360 op amp driving the reference pin. figure 7 shows a typical reference, the lt1019a-5 connected to the ltc1404. this will provide an improved figure 6. driving the v ref with the lt1360 op amp figure 7. supplying a 5v reference voltage to the ltc1404 with the lt1019a-5 drift (equal to the maximum 5ppm/ c of the lt1019a-5) and a 4.215v full scale. if v ref is forced lower than 2.43v, the refrdy bit in the serial data output will be forced to low. unipolar / bipolar operation and adjustment figure 8 shows the ideal input/output characteristics for the ltc1404. the code transitions occur midway between successive integer lsb values (i.e., 0.5lsb, 1.5lsb, 2.5lsb, ?fs ?1.5lsb). the output code is straight binary with 1lsb = 4.096v/4096 = 1mv. figure 9 shows the input/output transfer characteristics for the bipolar mode in two? complement format. unipolar offset and full-scale error adjustments in applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. figure 10a shows the extra components required for full-scale error adjustment. figure 10b shows offset and full-scale adjustment. offset error must be adjusted before full- scale error. zero offset is achieved by applying 0.5mv (i.e., 0.5lsb) at the input and adjusting the offset trim until the ltc1404 output code flickers between 0000 0000 0000 and 0000 0000 0001. for zero full-scale error, apply an analog input of 4.0945v (fs ?1.5lsb or last code transi- tion) at the input and adjust r5 until the ltc1404 output code flickers between 1111 1111 1110 and 1111 1111 1111. 1404 f06 + v ref(out) 2.46v a in v ref gnd 10 f 3 ? input range 0.843 ?v ref(out) 5v ?v ltc1404 lt1360 v cc v ss 1404 f07 10 f 3 ? input range 4.215v (= 0.843 ?v ref ) ?v lt1019a-5 10v v in v out gnd 5v a in v ref gnd ltc1404 v cc v ss
14 ltc1404 1404fa applicatio n s i n for m atio n wu u u figure 8. ltc1404 unipolar transfer characteristics input voltage (v) 0v output code fs ?1lsb 1404 f08 111...111 111...110 111...101 111...100 000...000 000...001 000...010 000...011 1 lsb unipolar zero 1lsb = fs 4096 4.096 4096 = figure 10b. ltc1404 offset and full-scale adjust circuit 1404 f10b + r2 10k r9 20 ? r4 100k r5 4.3k full-scale adjust r3 100k r6 400 ? r1 10k 10k analog input 0v to 4.096v a1 5v r8 10k offset adjust r7 100k 5v a in ltc1404 bipolar offset and full-scale error adjustments bipolar offset and full-scale errors are adjusted in a similar fashion to the unipolar case. bipolar offset error adjust- ment is achieved by applying an input voltage of 0.5mv ( 0.5lsb) to the input in figure 10c and adjusting the op amp until the adc output code flickers between 0000 0000 0000 and 1111 1111 1111. for full-scale adjustment, an input voltage of 2.0465v (fs ?1.5lsbs) is applied to the input and r5 is adjusted until the output code flickers between 0111 1111 1110 and 0111 1111 1111. 1404 f10c + r2 10k r4 100k r5 4.3k full-scale adjust r3 100k r6 200 ? r1 10k analog input 2.048v a1 r8 20k offset adjust r7 100k 5v ?v a in ltc1404 figure 10c. ltc1404 bipolar offset and full-scale adjust circuit figure 9. ltc1404 bipolar transfer characteristics input voltage (v) 0v output code ? lsb 1404 f09 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fs/2 ?1lsb fs/2 1404 f10a + r2 10k r3 10k r1 50 ? r4 100 ? full-scale adjust v in a1 ltc1404 a in gnd additional pins omitted for clarity 20lsb trim range figure 10a. ltc1404 full-scale adjust circuit
15 ltc1404 1404fa applicatio n s i n for m atio n wu u u board layout and bypassing to obtain the best performance from the ltc1404, a printed circuit board is required. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital traces alongside an analog signal trace or underneath the adc. the analog input should be screened by gnd. high quality 10 f surface mount avx capacitor with a 0.1 f ceramic should be used at the v cc , v ss and v ref pins. for better results, another 10 f avx capacitor can be added to the v cc pin. at 600ksps, the clk frequency can be as high as 9.6mhz. a poor quality capacitor can lose more than 80% of its capacitance at this frequency range. therefore, it is important to consult the manufacturer? data sheet before the capacitor is used. for the ltc1404, at 600ksps, every bit decision must be determined within 104ns (9.6mhz). during this short time interval, the supply disturbance due to a clk transition needs to settle. the adc must update its dac, make a comparator deci- sion based on sub-mv overdrive, latch the new dac information and output the serial data. this adc provides one power supply, v cc , which is connected to both the internal analog and digital circuitry. any ringing due to poor supply or reference bypassing, inductive trace runs, clk and conv over- or undershoot, or unnecessary d out loading can cause adc errors. therefore, the bypass capacitors must be located as close to the pins as possible. the traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. in unipolar mode operation, v ss must be con- nected to the gnd pin directly. input signal leads to a in and signal return leads from gnd (pin 4) should be kept as short as possible to minimize noise coupling. in applications where this is not possible, a shielded cable between the analog input signal and the adc is recommended. also, any potential difference in grounds between the analog signal and the adc appears as an error voltage in series with the analog input signal. attention should be paid to reducing the ground circuit impedance as much as possible. figure 11 shows the recommended system ground con- nections. all analog circuitry grounds should be termi- nated at the ltc1404 gnd pin. the ground return from the ltc1404 pin 4 to the power supply should be low imped- ance for noise free operation. digital circuitry grounds must be connected to the digital supply common. as an alternative, instead of a direct short between the digital and analog circuitry, a 10 ? or a ferrite bead jumper helps reduce the digital noise. analog supply 5v gnd 5v + + ltc1404 v ss v cc gnd digital supply gnd 5v + digital circuitry v cc gnd 1404 f11 figure 11. power supply connection in applications where the adc data outputs and control signals are connected to a continuously active micropro- cessor bus, it is possible to get errors in the conversion results. these errors are due to feedthrough from the microprocessor to the successive approximation com- parator. the problem can be eliminated by forcing the microprocessor into a wait state during conversion or by using three-state buffers to isolate the adc data bus. power-down mode upon power-up, the ltc1404 is initialized to the active state and is ready for conversion. however, the chip can be easily placed into nap or sleep mode by exercising the right combination of clk and conv signals. in nap mode, all power is off except for the internal reference, which is still active and provides 2.43v output voltage to the other circuitry. in this mode, the adc draws only 7.5mw of power instead of 75mw (for minimum power, the logic
16 ltc1404 1404fa applicatio n s i n for m atio n wu u u inputs must be within 500mv of the supply rails). in sleep mode, power consumption is reduced to 60 w by cutting off power to all internal circuitry including the reference. figure 12 illustrates power-down modes for the ltc1404. the chip enters nap mode by keeping the clk signal low and pulsing the conv signal twice. for sleep mode operation, the conv signal should be pulsed four times while clk is kept low. nap and sleep modes are activated on the falling edge of the conv pulse. the ltc1404 returns to active mode easily. the rising edge of clk wakes up the ltc1404. from nap mode, wake-up occurs within 350ns. during the transition from sleep mode to active mode, the v ref voltage ramp-up time is a function of its loading conditions. with a 10 f bypass capacitor, the wake-up time from sleep mode is typically 2.5ms. a refrdy signal is activated once the reference has settled and is ready for an a/d conversion. this refrdy bit is sent to the d out pin as the first bit followed by the 12-bit data word (refer to figure 13). to save power during wake-up from sleep mode, the chip is designed to enter nap mode automatically until the reference is ready. once refrdy goes high, the comparator powers up immediately and is ready for a conversion. during the nap interval, any attempt to perform an analog-to-digital con- version will result in an all-zero output code, including the refrdy bit. if no conversion is attempted, the d out pin remains in a high impedance state. if the adc wakes from sleep mode, this can be determined by monitoring the state of the refrdy bit at the d out pin. digital interface the digital interface requires only three digital lines. clk and conv are both inputs, and the d out output provides the conversion result in serial form. figure 13 shows the digital timing diagram of the ltc1404 during the a/d conversion. the conv rising edge starts the conversion. once initiated, it can not be restarted until the conversion is completed. if the time from conv signal to clk rising edge is less than t 2, the digital output will be delayed by one clock cycle. the digital output data is updated on the rising edge of the clk line. the digital output data consists of a refrdy bit followed by a valid 12-bit data word. d out data should be captured by the receiving system on the rising clk edge. data remains valid for a minimum time of t 10 after the rising clk edge to allow capture to occur. figure 12. nap mode and sleep mode waveforms clk conv nap sleep v ref t 1 t 1 t 11 refrdy hi-z hi-z hi-z hi-z all zero refrdy bit +12-bit data word refrdy = 0 d out note: nap and sleep are internal signals. refrdy appears as the first bit in the d out word 10 10 11 1 1404 f12 refrdy bit +12-bit data word refrdy = 1 t 11
17 ltc1404 1404fa figure 14. clk to d out delay applicatio n s i n for m atio n wu u u clk conv internal s/h status d out t 7 t 3 12345678910111213 14 15 16 1 2 t 2 t 6 t 4 t 5 t 8 t acq sample sample hold hold refrdy bit + 12-bit data word hi-z hi-z t conv t sample 1404 f13 refrdy d11 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d10 refrdy figure 13. adc digital timing diagram t 10 t 8 v ih v oh v ol d out clk t 9 v ih 90% 10% d out clk 1404 f14
18 ltc1404 1404fa typical applicatio n s u v cc a in v ref v ss clk conv d out gnd tclkx tclkr tfsx tfsr tdr ltc1404 tms320c50-40mhz + 10 f 0.1 f unipolar input 7.8mhz external clock + 10 f 0.1 f 5v 1404 ta04a 1 2 3 84 6 7 5 hardware interface to the tms320c50? tdm serial port (frame sync is generated from tfsx) logic analyzer waveforms show 2.05 s throughput rate (input voltage = 1.606v, output code = 0110 0100 0110 = 1606 10 ) d0 x x 1404 ta04c d1 d2 d4 d5 d3 rdy x d11 d10 d9 d8 d7 d6 d2 d1 d0 1404 ta04d d3 d4 d6 d7 d5 0 0 0 rdy d11 d10 d9 d8 note: the tms320c50-40mhz has a limited serial port clock speed of 7.8mhz. to allow the ltc1404 to run at its maximum speed of 9.6mhz, the tms320c50-57 or tms320c50-80mhz is needed data from the ltc1404 loaded into the tms320c50? trcv register data stored in the tms320c50? memory (in right justified format) 1404t a04b
19 ltc1404 1404fa typical applicatio n s u tms320c50 code for circuit this program demonstrates the ltc1404 interface to the tms320c50. frame sync pulse is generated from tfsx. data shift clock is externally generated. *initialization* .mmregs ; defines global symbolic names ;- - initialized data memory to zero .ds 0f00h ; initialize data to zero data0 .word 0 ; begin sample data location data1 .word 0 ; . data2 .word 0 ; location of data data3 .word 0 ; . data4 .word 0 ; . data5 .word 0 ; end sample data location ;- - set up the isr vector .ps 080ah ; serial ports interrupts rint : b receive ; 0a; xint : b transmit ; 0c; trnt : b trec ; 0e; txnt : b ttranx ; 10; ;- - setup the reset vector .ps 0a00h .entry start: *tms320c50 initialization* setc intm ; temporarily disable all interrupts ldp #0 ; set data page pointer to zero opl #0834h, pmst ; set up the pmst status and control register lacc #0 samm cwsr ; set software wait state to 0 samm pdwsr ; *configure serial port* splk #0028h, tspc ; set tdm serial port ; tdm = 0 stand alone mode ; dlb=0 not loop back ; fo=0 16 bits ; fsm=1 burst mode ; mcm=0 clkr is generated externally ; txm=1 fsx as output pin ; put serial port into reset ; (xrst=rrst=0) splk #00e8h, tspc ; take serial port out of reset ; (xrst=rrst=1) splk #0ffffh, ifr ; clear all the pending interrupts *start serial communication* sacl tdxr ; generate frame sync pulse splk #040h, imr ; turn on trnt receiver interrupt clrc intm ; enable interrupt clrc sxm ; for unipolar input, set for right shift ; with no sign extension mar *, ar7 ; load the auxiliary register pointer with seven lar ar7, #0f00h ; load the auxiliary register seven with #0f00h ; as the begin address for data storage wait: nop ; wait for a receive interrupt nop ; nop ; sacl tdxr ; !! regenerate the frame sync pulse b wait ; ; - - - - - - - end of main program - - - - - - - - - - ; *receiver interrupt service routine* trec: lamm trcv ; load the data received from ltc1404 sfr ; shift right two times sfr ; and #1fffh, 0 ; anded with #1fffh ; for converting the data to right ; justified format ; sacl *+, 0 ; write to data memory pointed by ar7 and ; increase the memory address by one lacc ar7 ; sub #0f05h,0 ; compare to end sample address #0f05h bcnd end_trcv, geq ; if the end sample address has exceeded jump to end_trcv ; splk #040h, imr ; else re-enable the trnt receive interrupt rete ; return to main program and enable interrupt *after obtained the data from ltc1404, program jump to end_trcv* end_trcv: splk #002h, imr ; enable int2 for program to halt clrc intm success: b success *fill the unused interrupt with rete, to avoid program get ?ost? ttranx: rete receive: rete transmit: rete int2: b halt ; halts the running cpu
20 ltc1404 1404fa typical applicatio n s u ltc1404 interface to the adsp2181? sport0 (frame sync is generated from rfs0) data stored in the adsp2181? memory (normal mode, slen = d) d2 d1 d0 d3 d4 d6 d7 d5 0 0 0 rdy d11 d10 d9 d8 1404 ta05d d0 x x d1 d2 d4 d5 d3 rdy x d11 d10 d9 d8 d7 d6 1404 ta05c data from the ltc1404 (normal mode) logic analyzer waveforms show 1.67 s throughput rate (input voltage = 1.604v, output code = 0110 0100 0100 = 1604 10 ) 1404 ta05b note: without the external clocking signal, the adsp2181 sclk0 can be programmed to run at 8.3mhz a in v ss v cc v ref clk conv d out gnd sclko rfso dr0 ltc1404 adsp2181 9.6mhz external clock unipolar input + 10 f 0.1 f + 10 f 5v 0.1 f 1 2 3 84 6 7 5 1404 ta05a
21 ltc1404 1404fa typical applicatio n s u this program demonstrates the ltc1404 interface to the adsp-2181. frame sync pulse is generated from rfs. data shift clock is externally generated. /*section 1: initialization*/ .module/ram/abs = 0 adspltc; /*define the program module*/ jump start; /*jump over interrupt vectors*/ nop; nop; nop; rti; rti; rti; rti; /*code vectors here upon irq2 int*/ rti; rti; rti; rti; /*code vectors here upon irql1 int*/ rti; rti; rti; rti; /*code vectors here upon irql0 int*/ rti; rti; rti; rti; /*code vectors here upon sport0 tx int*/ ax0 = rx0; /*section 5*/ dm (0x2000) = ax0; /*begin of sport0 receive interrupt*/ rti; /* */ /* */ /*end of sport0 receive interrupt*/ rti; rti; rti; rti; /*code vectors here upon /irqe int*/ rti; rti; rti; rti; /*code vectors here upon bdma interrupt*/ rti; rti; rti; rti; /*code vectors here upon sport1 tx (irq1) int*/ rti; rti; rti; rti; /*code vectors here upon sport1 rx (irq0) int*/ rti; rti; rti; rti; /*code vectors here upon timer int*/ rti; rti; rti; rti; /*code vectors here upon power down int*/ /*section 2: configure sport0*/ start: /*to configure sport0 control reg*/ /*sport0 address = 0x3ff6*/ /*rfs is used for frame sync generation*/ /*rfs is internal, tfs is not used*/ /*bit 0-3 = slen*/ /*f = 15 = 1111*/ /*e = 14 = 1110*/ /*d = 13 = 1101*/ /*bit 4,5 data type right justified zero filled msb*/ /*bit 6 invrfs = 0*/ /*bit 7 invtfs = 0*/ /*bit 8 irfs=1 receive internal frame sync*/ /*bit 9,10,11 are for tfs (don? care)*/ /*bit 12 rfsw=0 receive is normal mode*/ /*bit 13 rtfs=1 receive is framed mode*/ /*bit 14 isclk=0 sclk is external */ /*bit 15 multichannel mode = 0*/ ax0 = 0x2f0d; /*normal mode, bit 12=0*/ /*if alternate mode bit 12=1, ax0=0x3f0e*/ dm (0x3ff6) =ax0; /*section 3: configure clkdiv and rfsdiv, setup interrupts*/ /*using an external clock source=9.6mhz*/ /*does not need to configure clkdiv*/ /*to configure rfsdiv*/ ax0 = 15; /*set the rfsdiv reg = 15*/ /*=> the frame sync pulse for every 16 sclk*/ /*if frame sync pulse in every 15 sclk, ax0=14*/ dm(0x3ff4) =ax0; /*to setup interrupt*/ ifc= 0x0066; /*clear any extraneous sport interrupts*/ icntl= 0; /*irqxb = level sensitivity*/ /*disable nesting interrupt*/ imask= 0x0020; /*bit 0 = timer int = 0*/ /*bit 1 = sport1 or irq0b int = 0*/ /*bit 2 = sport1 or irq1b int = 0*/ /*bit 3 = bdma int = 0*/ /*bit 4 = irqeb int = 0*/ /*bit 5 = sport0 receive int = 1*/ /*bit 6 = sport0 transmit int = 0*/ /*bit 7 = irq2b int = 0*/ /*enable sport0 receive interrupt*/ /*section 4: configure system control register and start communication*/ /*to configure system control reg*/ ax0 = dm(0x3fff); /*read the system control reg*/ ay0 = 0xfff0; ar = ax0 and ay0; /*set wait state to zero*/ ay0 = 0x1000; ar = ar or ay0; /*bit 12 = 1, enable sport0*/ dm(0x3fff) = ar; /*frame sync pulse regenerated automatically*/ cntr = 5000; do waitloop until ce; nop; nop; nop; nop; nop; nop; waitloop: nop; rts; .endmod; adsp2181 code for circuit
22 ltc1404 1404fa typical applicatio n s u 1 8 ltc1404 conv clk d out gnd analog input (0v to 4.096v) 12 11 14 13 15 1 2 3 4 5 6 7 9 qa qb qc qd qe qf qg qh qh' d0 d1 d2 d3 d4 d5 d6 d7 rck srck ser g 0.1 f 10 f + 10 f 0.1 f 2.43v reference output + srclr 74hc595 10 12 11 14 13 15 1 2 3 4 5 6 7 9 qa qb qc qd qe qf qg qh qh' d8 d9 d10 d11 refrdy rck srck ser g srclr 74hc595 10 clk conv 3-wire serial interface link 5v 1404 ta03 5v 3 v ref 4 2 v cc v ss a in 7 6 5 quick look circuit for converting data to parallel format
23 ltc1404 1404fa package descriptio n u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. .016 ?.050 (0.406 ?1.270) .010 ?.020 (0.254 ?0.508) 45 0 ?8 typ .008 ?.010 (0.203 ?0.254) so8 0303 .053 ?.069 (1.346 ?1.752) .014 ?.019 (0.355 ?0.483) typ .004 ?.010 (0.101 ?0.254) .050 (1.270) bsc 1 2 3 4 .150 ?.157 (3.810 ?3.988) note 3 8 7 6 5 .189 ?.197 (4.801 ?5.004) note 3 .228 ?.244 (5.791 ?6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610)
24 ltc1404 1404fa ? linear technology corporation 1998 lt 0506 rev a ?printed in usa typical applicatio n s u ltc1404 interface to tms320c50 running at 5mhz without external clock ltc1404 interface to adsp2181 running at 8.3mhz without external clock related parts a in v ss v cc v ref clk conv d out gnd sclko rfso dr0 ltc1404 adsp2181 unipolar input + 10 f 0.1 f + 10 f 5v 0.1 f 1 2 3 84 6 7 5 1404 ta06 (8.3mhz) v cc a in v ref v ss clk conv d out gnd tclkx tclkr tfsx tfsr tdr ltc1404 tms320c50 + 10 f 0.1 f unipolar input + 10 f 0.1 f 5v 1404 ta07 1 2 3 84 6 7 5 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com part number description comments ltc1285/ltc1288 12-bit, 3v, 7.5/6.6ksps, micropower serial adcs 0.48mw, 1-/2-channel input, so-8 ltc1286/ltc1298 12-bit, 5v, 12.5/11.16ksps, micropower serial adcs 1.25mw, 1-/2-channel input, so-8 ltc1290 12-bit, 50ksps 8-channel serial adc 5v or 5v input range, 30mw, full-duplex ltc1296 12-bit, 46.5ksps 8-channel serial adc 5v or 5v input range, 30mw, half-duplex ltc1403/ltc1403a 12-/14-bit 2.8msps serial adcs 3v, 15mw, msop-10 package, unipolar input ltc1403-1/ltc1403a-1 12-/14-bit, 2.8msps serial adcs 3v, 15mw, msop-10 package, bipolar input ltc1407/ltc1407a 12-/14-bit, 3msps simultaneous sampling adcs 3v, 14mw, 2-channel unipolar differential inputs, msop-10 ltc1407-1/ltc1407a-1 12-/14-bit, 3msps simultaneous sampling adcs 3v, 14mw, 2-channel bipolar differential inputs, msop-10 ltc1417 14-bit, 400ksps serial adc 5v or 5v, 20mw, internal reference, ssop-16 ltc1609 16-bit, 200ksps serial adc 5v, configurable bipolar or unipolar inputs to 10v ltc1860l/ltc1861l 12-bit, 3v, 150ksps serial adcs 1.22mw, 1-/2-channel input, msop-8 and so-8 ltc1860/ltc1861 12-bit, 5v, 250ksps serial adcs 4.25mw, 1-/2-channel input, msop-8 and so-8 ltc1864l/ltc1865l 16-bit, 3v, 150ksps serial adcs 1.22mw, 1-/2-channel input, msop-8 and so-8 ltc1864/ltc1865 16-bit, 5v, 250ksps serial adcs 4.25mw, 1-/2-channel input, msop-8 and so-8

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